High Speed and Low Offset Comparator For A/D Converter

In high speed ADC, speed limiting element is comparator. This paper describes a very high speed and low offset preamplifierlatch comparator. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are good. Based on TSMC 0.18um CMOS process model, simulated results show the comparator can work under ultra high speed clock frequency 1GHz Keywords-—high speed ADC, high speed comparator, preamplifier latch comparator, low offset comparator Introduction: Recently several high-speed, high-resolution CMOS pipelined A/D converters with the operational frequency up to MHz have been reported [1][2]. ADCs are widely used in many applications including data storage systems, fast serial links and high-speed measurement instruments The preamplifier latch comparator [1][2,], combine the application of both comparator. To enhance the performance of A/D converter. In this paper, an architecture for a highspeed comparator is presented . In high speed analog-to-digital converters, the performance of comparator, especially speed and resolution has a crucial influence on the overall performance that can be achieved by using preamplifier, kickback and latch stage. The comparator senses the charge imbalance produced by the input at the preamplifier and reacts to that imbalance to create desired digital voltage levels at the output. DESIN Of PREAMPLIFIER LATCH COMPARATOR PRE-AMPLIFIER The pre-amplifier used in this design is a simple common source differential amplifier with PMOS transistors as active loads. Pre-amplifier is followed by a small circuit which is basically used for two main functions. First it is used to avoid the kick back effect from the latch to the input signal which is made possible by using two NMOS transistors which operation on the clock. Kick back is the noise observed at the input signal which is produced due to high voltage variations at the regenerative nodes of the latched and is coupled to the input through the parasitic capacitance of the transistors. The second purpose of using the kick back protection circuitry is to create charge imbalance in the latch when it switches from reset mode to regeneration mode. There are several types of comparator can provide the high speed, such as cmos comparator, the conventional three stage comparator, regenerative latch comparator and preamplifier latch comparator. Open loop comparator can obtain high speed by cascading several stage. Speed is more then 1GSPS is limited by the bandwidth of amplifier. Dynamic latch comparator have high speed but poor resolution because of higher offset Complete circuit diagram of the latched comparator Vin (+) and Vin (-) are the two input signals for the pre-amplifier C1. The change in these two signals is amplified by the per-amplifier. From the pre-amplifier, the amplified voltage difference is transferred to the gates of the circuit C2. C2 is a small circuit that creates charge imbalance in the latch and minimizes the kickback noise effects from latch to the pre-amplifier. The latch operates in two phases; reset and regeneration. In the reset phases the charge imbalance is created on the differential nodes of the latch proportional to the variation in the input signal. In regenerator mode, the voltage imbalance on the nodes is amplified to the rail-to-rail digital levels by the NMOS and PMOS regeneration loops. SPEED OF THE COMPARATOR Speed of the comparator is highly dependant on the regenerative time constant of the latch. We can model the latch with two inverters connected in the loop with positive feed back configuration as shown in figure 2